Synopsys has launched its DesignWare High-Performance Core Design Kit for EV6x Processors to help designers meet the performance, power, and area requirements of their systems-on-chips for embedded vision and artificial intelligence applications.
The DesignWare HPC Design Kit, a suite of high-speed and high-density memories and specialized logic libraries, allows SoC designers to optimize the EV6x processor’s vector DSPs and convolutional neural network engines for maximum speed, smallest area, lowest power, or an optimum balance of the three.
Depending on the requirements of the target application, designers using the HPC Design Kit for EV6x can optimize their implementation to achieve a 39 percent power reduction, a 10 percent reduction in area, or a 7 percent performance boost for their SoCs.
The new HPC Design Kit for the EV6x Embedded Vision Processors contains fast cache memory instances, ultra-high-density two-port SRAMs, and a suite of cells including multi-bit flip-flops, compressors, and multiplexers that enable designers to optimize their SoCs’ processors and reduce their time-to-tapeout.
Options for overdrive/low-voltage process, voltage, and temperature corners, multi-channel cells, and memory built-in self-test and repair are also available.
Optimized design flow scripts and expert core optimization consulting, including FastOpt implementation services, are available to help design teams achieve their processor and SoC design goals in the shortest possible time.
John Koeter, vice president of marketing for IP at Synopsys, says: “The physical IP used for implementing processors into intelligent systems has significant impact on the performance, power, and area of the design.
“The combination of the DesignWare HPC Design Kit and EV6x Vision Processors enables designers to optimize the cores across the full speed, power, and area spectrum to meet the specific requirements of their SoCs.”