IBM and Synopsys accelerate 3 nanometer process for chip development
IBM and Synopsys are working together within the so-called “DTCO methodology” to accelerate the development of 3 nanometer chips.
Microchips these days tend to have transistors of around 10 nanometers, with 7 nanometer and smaller processes being developed.
Any smaller could cause problems of making things work properly.
But IBM and Synopsys are partnering through something called the “Design Technology Co-Optimization” methodology.
Synopsys says it is collaborating with IBM to apply design technology DTCO to the pathfinding of new semiconductor process technologies “for the 3-nanometer process node and beyond”.
DTCO is a methodology for efficiently evaluating and down-selecting new transistor architectures, materials and other process technology innovations using design metrics, starting with an early pathfinding phase before wafers become available.
The collaboration will extend the current Synopsys DTCO tool flow to new transistor architectures and other technology options while enabling IBM to develop early process design kits for its partners to assess the power, performance, area, and cost benefits at IBM’s advanced nodes.
Dr Mukesh Khare, vice president of semiconductor research, IBM Research Lab, says: “Process technology development beyond 7 nanometers requires the exploration of new materials and transistor architectures to achieve optimum manufacturability, power, performance, area, and cost.
“A major challenge for foundries is to converge on the best architecture in a timely manner while vetting all the possible options.
“Our DTCO collaboration with Synopsys allows us to efficiently select the best transistor architecture and process options based on metrics derived from typical building blocks, such as CPU cores, thus contributing to faster process development at reduced cost.”
In this collaboration, IBM and Synopsys are developing and validating new patterning techniques with Proteus mask synthesis, modeling new materials with QuantumATK, optimizing new transistor architectures with Sentaurus TCAD and Process Explorer, and extracting compact models with Mystic.
Design rules and process assumptions derived from these process innovations are used to design and characterize a standard cell library while Fusion Technology at the block level using the Synopsys physical implementation flow based on IC Compiler II place-and-route, StarRC extraction, SiliconSmart characterization, PrimeTime signoff, and IC Validator physical verification benefits the evaluation of PPAC.
The scope of the joint development agreement covers multiple facets, including:
- DTCO to optimize transistor- and cell-level design across routability, power, timing, and area
- Evaluate and optimize new transistor architectures, including gate-all-around nanowire and nanoslab devices, with process and device simulation
- Optimize variation-aware models for SPICE simulation, parasitic extraction (PEX), library characterization, and static timing analysis (STA) to accurately encapsulate the effects of variation on timing and power for highest-reliability design with least over-design and design flow runtime overhead
- Gather gate-level design metrics to refine the models, library architecture, and design flows to maximize PPAC benefits
Dr Antun Domic, chief technology officer at Synopsys, says: “Synopsys has developed the only complete DTCO solution, from materials exploration to block-level physical implementation.
“IBM’s extensive process development and design know-how makes them an ideal partner for extending our DTCO solution to 3 nanometers and beyond.”
